Customized IC Solutions for
Military and Space Applications

Trusted Semiconductor Solutions' IC Design Solution

Trusted Semiconductor Solutions’ engineering design team includes in-house and third party industry experts in ASIC and custom IC development. These designers will work along side your system and ASIC designers to develop products that meet specifications, are delivered on-time, and within the established budgets.

We provide services from architecture development through GDSII tape-out. Our design team has experience designing for CMOS, BiCMOS, Bipolar, GaAs, and SiGe process technology with geometries down to 65nm. We also have experience designing for radiation sensitive environments. Our design experience includes high-speed digital communication protocols, DC to RF analog design, mixed signal IC, DSP, microcontroller design, embedded custom IP integration (such as PowerPC, ARM or MIPs), design for test and verification, and low power, high performance IC design.

Our design services start with your written or oral specifications. We will work with you to clearly define the system and IC specifications. It is important to clearly define the IC so that it can be partitioned correctly, designed for reuse and include design for test and verification. We will also define the success criteria for the program at this time. It is of utmost importance that we understand your needs and meet your expectations.

Once the project specifications have been set, we will hold a preliminary design review. This will allow us to mutually agree on the specifications and scope of the design and allow our designers to commence on architecting your system. Our engineers are experienced in design capture in VHDL and Verilog, as well as custom logic development. We utilize the latest EDA technology and methodologies to ensure a quality design.

We incorporate physical design into the first steps of design architecture to make sure power and performance requirements are met. Our team is experienced in floorplanning, physical layout and final design checking so that a GDSII netlist can be created for release to fab.